The present invention relates to a memory system composed of an electrically erasable and programmable multi-level data storage nonvolatile semiconductor memory device (EEPROM).
In recent years, a NAND cell EEPROM has been suggested as one of electrically erasable and programmable nonvolatile semiconductor memory devices.
A NAND cell EEPROM is arranged such that a plurality of memory cells, each comprising a stacked gate type n-channel FETMOS structure with a floating gate and a control gate, are connected in series. The series-connected memory cells constitute one unit and are connected to a bit line.
FIG. 38A is a plan pattern view showing one NAND cell of a memory cell array, and FIG. 38B is a circuit diagram of the NAND cell. FIG. 39A is a cross sectional view taken along line XXXIXA--XXXIXA shown in FIG. 38A, and FIG. 39B is a cross sectional view taken along line XXXIXB--XXXIXB shown in FIG. 38A.
A p-type silicon substrate (or a p-type well) 11 has a surface having a device region surrounded by a device isolating oxide film 12. A NAND cell is formed in each device region. A plurality of NAND cells form one memory cell array.
Referring to FIGS. 38A, 38B, 39A and 39B, one of the NAND cells will now be described.
A semiconductor apparatus shown in FIGS. 38A, 38B, 39A and 39B has eight memory cells M1 to M8 connected in series to form one NAND cell. Each memory cell has a floating gate 14 (14-1, 14-2, . . . , 14-8) formed on a substrate 11 through a gate insulating film 13. A control gate 16 (16-1, 16-2, . . . , 16-8) is formed on the floating gate 14 through a second gate insulating film 15. An n-type diffusion layer 19, which is the source/drain of the memory cell is shared by adjacent memory cells. Thus, the eight memory cells are connected in series.
The NAND cell has, in the drain portion, first selection gates 14-9 and 16-9, and in the source portion, second selection gates 14-10 and 16-10, formed simultaneously with the floating gates 14-1 to 14-8 and the control gates 16-1 to 16-8. The substrate 11 having the devices, such as the memory cells, is covered with a CVD oxide film 17. A bit line 18 is disposed above the CVD oxide film 17. The control gates 16 of the NAND cell are formed to extend in the row direction to be made common with control gates of the corresponding memory cells of the NAND cell adjacent in the direction of the row to serve as word lines (control gates CG1, CG2, . . . , CG8). The selection gates 14-9 and 16-9 and the selection gates 14-10 and 16-10 are formed to extend in the direction of the row, in a manner similar to the control gates 16-1 to 16-8, to be made common with the corresponding selection gates of a NAND cell adjacent in the direction of the row to serve as selection gates SG1 and SG2.
FIG. 40 is a circuit diagram showing a memory cell array having the NAND cells disposed in a matrix configuration.
As shown in FIG. 40, the source line is, through a contact, connected to a reference potential line made of aluminum or conductive polysilicon. The contact between the source line and the reference potential line is provided for each 64 bit lines. The reference potential line is connected to a peripheral circuit (not shown) which controls, for example, the potential to be applied to the source line to correspond to the operation mode.
The first and second selection gates SG1 and SG2 of the control gates CG1, CG2, . . . , CG8 are formed to extend in the direction of the row. A set of memory cells connected to one control gate is, in general, called a page (one page), and a set of the pages held between one set of drain side (the first selection gate) and source side (the second selection gate) selection gates is called a NAND block (one NAND block) or a block (one block). One page is composed of, for example, 256 byte (256.times.8) memory cells. Writing of data is substantially simultaneously performed on the memory cells for one page. One block is composed of, for example, 2048 byte (2048.times.8) memory cells. Data is substantially simultaneously erased from the memory cells for one block.
The operation of the NAND EEPROM is performed as follows.
Writing of data is sequentially performed while starting at the farthest memory cell from the bit line.
Raised writing voltage Vpp (=about 20 V) is applied to the control gate of the selected memory cell, an intermediate potential (=about 10 V) is applied to the control gates of the non-selected memory cells and the first selection gates and 0 V (writing of "0") or an intermediate potential (writing of "1") is applied to the bit line in accordance with data. At this time, the potential of the bit line is transmitted to the selected memory cell. When data is "0", high voltage is applied between the floating gate of the selected memory cell and the substrate so that electrons are tunnel-implanted from the substrate into the floating gate so that the threshold voltage is shifted in the positive direction. When data is "1", the threshold voltage is not changed.
Erase of data is performed substantially simultaneously in block units.
That is, when data is erased, all of the control gates and selection gates included in the blocks from which data is erased are made to be 0 V, and then raised potential VppE (about 20 V) is applied to the p-type silicon substrate (or the p-type well formed on the n-type substrate). The raised potential VppE is applied to the control gates and selection gates included in the blocks from which data is not erased. As a result, in the memory cells in the blocks from which data is erased, electrons stored in the floating gate are discharged to the p-type silicon substrate (or the p-type well) so that the threshold voltage is shifted in the negative direction.
The operation for reading data is performed such that the bit line is precharged, and then the bit line is brought to a floating state. Then, the control gate of the selected memory cell is made to be 0 V, the control gates of the other memory cells and the selection gates are made to be power supply voltage Vcc (for example, 3 V) and the source line is made to be 0 V. As a result, whether or not an electric current flows in the selected memory cell is detected in accordance with change in the potential of the bit line. That is, if data written on the memory cell is "0" (if the threshold value of the memory cell satisfies Vth&gt;0), the memory cell is turned off so that the bit line maintains the precharge potential. If data is "1" (if the threshold value of the memory cell satisfies Vth&lt;0), the memory cell is turned on so that an electric current flows to cause the potential of the bit line to be lowered by *1 V from the precharge potential. The potential of the bit line is detected by a sense amplifier so that data in the memory cell is read.
In recent years, a multi-level data storage cell structured such that information of three or more levels is stored in one cell has been known as one method capable of realizing a EEPROM having a large capacity (for example, refer to Japanese Patent Laid-Open No. 7-93979 and Japanese Patent Laid-Open No. 7-161852).
FIG. 41 is a graph showing the relationship between the threshold voltages of a memory cell and four writing states (four value data "0", "1", "2" and "3").
The state of data "0" is similar to the state after data has been erased and has, for example, a negative threshold value. The state of data "1" has a threshold voltage in a range from, for example, 0.5 V to 0.8 V. The state of data "2" has a threshold voltage in a range from, for example, 1.5 V to 1.8 V. The state of data "3", has a threshold voltage in a range from, for example, 2.5 V to 2.8 V.
Therefore, reading voltage VCG2R is applied to the control gate CG to detect whether the memory cell is turned on or off so as to detect whether data in the memory cell is "0" or "1" and whether the same is "2" or "3". In accordance with a result of the foregoing detection, reading voltage VCG3R or VCG1R is applied so that data in the memory cell is detected. The reading voltages VCG1R, VCG2R and VCG3R are, for example, 0 V, 1 V and 2 V, respectively.
The voltages VCG1V, VCG2V and VCG3V are called verify voltages. When data is written, the verify voltages are applied to the control gate to detect the data writing state on the memory cell M, that is, whether or not data has been sufficiently written. The verify voltages VCG1V, VCG2V and VCG3V are, for example, 0.5 V, 1.5 V and 2.5 V, respectively.
A flash memory involves a limited number of times of write-erase sequence such that, for example, the number of times of write-erase sequence for a two-level memory cell is limited to 1,000,000 times. The limitation of the number of times of write-erase sequence arises when electrons stored in the floating gate leak from the floating gate of the memory cell in the write state to the substrate if further write-erase sequence is performed. When electrons are leaked from the memory cell in the state of data 1 shown in FIG. 41 and thus the memory cell is brought to the state of data "0", written data is broken.
When multi-level data is stored in the memory cell, the difference between the multi-level data (for example, the difference in the voltage between the state "3" and the state "2" shown in FIG. 41) is reduced. As a result, if electrons in a slight quantity are leaked to the substrate, data in the state "3" is unintentionally changed to the state "2". If the memory cell is brought to the multi-level data mode, the threshold value of the highest threshold voltage (the state "3" in a state shown in FIG. 41) must be enlarged. Therefore, the electric field between the floating gate and the substrate is enlarged, thus causing the quantity of electrons leaked from the floating gate to be enlarged.
Under these circumstances, the more the number of data levels of the memory cell becomes, the more the reliability to the number of times of write-erase sequence deteriorates. Therefore, the number of permitted times of write-erase sequence is reduced to, for example, 500,000 times. As a result, the durability (the lifetime) of the semiconductor device deteriorates.
A conventional memory card (for example, refer to Niijima; IBM J. RES. DEVELOP. VOL. 39, No. 5 SEPTEMBER 1995) has a structure such that the number of times of write-erase sequence is recorded for each block and a block subjected to 1,000,000 times or more write-erase sequence operations is not used. However, also the foregoing method involves the number of times permitted for the memory card to be used being reduced as compared with the 2-level data memory mode when the number of the data levels is increased.